For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip
Chaochao FENG Zhonghai LU Axel JANTSCH Minxuan ZHANG
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/05/01
Online ISSN: 1745-1361
Print ISSN: 0916-8532
Type of Manuscript: LETTER
Category: Computer System
3D NoC, bufferless router, permutation network,
Full Text: PDF(369.5KB)
>>Buy this Article
In this paper, we propose a 1-cycle high-performance 3D bufferless router with a 3-stage permutation network. The proposed router utilizes the 3-stage permutation network instead of the serialized switch allocator and 77 crossbar to achieve the frequency of 1.25 GHz in TSMC 65 nm technology. Compared with the other two 3D bufferless routers, the proposed router occupies less area and consumes less power consumption. Simulation results under both synthetic and application workloads illustrate that the proposed router achieves less average packet latency than the other two 3D bufferless routers.