A C-Testable Multiple-Block Carry Select Adder

Nobutaka KITO  Shinichi FUJII  Naofumi TAKAGI  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E95-D   No.4   pp.1084-1092
Publication Date: 2012/04/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E95.D.1084
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Dependable Computing
Keyword: 
carry select adder,  design for testability,  C-testability,  

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Summary: 
We propose a C-testable multiple-block carry select adder with respect to the cell fault model. Full adders and 2:1 multiplexers are considered as cells. By an additional external input, we obtain a C-testable carry select adder. We only modify the least significant position of each block. The adder is testable with a test set consisting of 16 patterns regardless of the size of each block and the number of blocks. This is the minimum test set for the adder. We show two gate-level implementations of the adder which are testable with a test set of 9 patterns and 7 patterns respectively, with respect to the single stuck-at fault model.