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A Pulse-Generator-Free Hybrid Latch Based Flip-Flop (PHLFF)
IEICE TRANSACTIONS on Electronics Vol.E95-C No.6 pp.1125-1127
Publication Date: 2012/06/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: BRIEF PAPER
Category: Electronic Circuits
pulse generator free,
Full Text: PDF(255.9KB)
A novel hybrid latch based flip-flop scheme is introduced in this paper. A pulse generator is eliminated to simplify clock distribution and save power. It also achieves high speed by shortening the critical data path. In addition, it avoids output node glitches which exist in conventional hybrid latch based flip-flops. HSPICE simulation results revealed that the proposed PHLFF performs best among referenced schemes. It can reduce 47.5% power dissipation, 16.5% clock-to-output latency and 56.4% PDP, as compared to conventional HLFF.