CMOS Differential Circuits Using Charge-Redistribution and Reduced-Swing Schemes

Hong-Yi HUANG  Shiun-Dian JAN  Yang CHOU  Cheng-Yu CHEN  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E95-C   No.2   pp.275-283
Publication Date: 2012/02/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E95.C.275
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword: 
differential logic,  charge redistribution,  low power,  high speed,  multiplier-accumulator,  

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Summary: 
The charge-redistribution low-swing differential logic (CLDL) circuits are presented in this work. It can implement a complex function in a single gate. The CLDL circuits utilizes the charge-redistribution and reduced-swing schemes to reduce the power dissipation and enhance the operation speed. In addition, a pipeline structure is formed by a series connection structure controlled by a true-single-phase clock, thereby achieving high-speed operation. The CLDL circuits perform more than 25% speedup and 31% in power-delay product compared to other differential circuits with true-single-phase clock. A pipelined multiplier-accumulator (MAC) using CLDL structure is fabricated in 0.35 µm single-poly four-metal CMOS process. The test chip is successfully verified to operate at 900-MHz.