0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65 nm CMOS

Yasuyuki OKUMA  Koichi ISHIDA  Yoshikatsu RYU  Xin ZHANG  Po-Hung CHEN  Kazunori WATANABE  Makoto TAKAMIYA  Takayasu SAKURAI 

Publication
IEICE TRANSACTIONS on Electronics  Vol.E94-C  No.6  pp.938-944
Publication Date: 2011/06/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
low dropout regulator,  digital control,  low voltage, 

Full Text: PDF

Summary: 
In this paper, Digital Low Dropout Regulator (LDO) is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5 V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65 nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-µA quiescent current at 200-µA load current. Both the input voltage and the quiescent current are the lowest values in the published LDO's, which indicates the good energy efficiency of the digital LDO at 0.5-V operation.