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A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests
Shunichi KAERIYAMA Mikihiro KAJITA Masayuki MIZUNO
IEICE TRANSACTIONS on Electronics
Publication Date: 2011/01/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
clock generator, duty ratio, frequency synthesis, I/Q balance, jitter, timing margin,
Full Text: PDF(2.3MB)>>
A 4-phase clock generator, which can dynamically change clock frequencies, duty ratios and I/Q balance, is proposed for on-chip timing margin testing. The clock generator macro is integrated into the microprocessor chip of the supercomputer SX-9, which is fabricated with a 65 nm CMOS technology. It demonstrates frequency syntheses of 1.68 GHz to 3 GHz range, an instant frequency change capability for timing margin testing, duty ratio and I/Q balance adjustments of -12.5 ps to 9.4 ps with a 3.125 ps step resolution.