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Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E94-A No.12 pp.2499-2509
Publication Date: 2011/12/01
Online ISSN: 1745-1337
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Full Text: PDF
Beyond deep sub-micron era, Power Gating (PG) is one of the most effective techniques to reduce leakage power of circuits. The most important issue of PG circuit design is how to decide the width of sleep transistor. Smaller total sleep transistor width provides smaller leakage power in standby mode, however, insufficient sleep transistor insertion suffers from significant performance degradation. In this paper, we present an accurate and fast gate-level delay estimation method for PG circuits and a novel sleep transistor sizing method utilizing our delay estimation for module-based PG circuits. This method achieves high accuracy within acceptable computation time utilizing accurate discharge current estimation based on delayed logic simulations with limited input vector patterns and by realizing precise current characteristics for logic gates and sleep transistors. Experimental results show that our delay estimation successfully achieves high accuracy and avoids overestimation and underestimation seen in conventional method. Also, our sleep transistor sizing method on average successfully reduces the width of sleep transistors by 40% when compared to conventional methods within an acceptable computation time.