Multiple-Valued Constant-Power Adder and Its Application to Cryptographic Processor

Naofumi HOMMA  Yuichi BABA  Atsushi MIYAMOTO  Takafumi AOKI  

IEICE TRANSACTIONS on Information and Systems   Vol.E93-D   No.8   pp.2117-2125
Publication Date: 2010/08/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E93.D.2117
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Application of Multiple-Valued VLSI
cryptographic processors,  side-channel attacks,  arithmetic circuits,  multiple-valued logic,  RSA cryptosystem,  

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This paper proposes a constant-power adder based on multiple-valued logic and its application to cryptographic processors being resistant to side-channel attacks. The proposed adder is implemented in Multiple-Valued Current-Mode Logic (MV-CML). The important feature of MV-CML is that the power consumption can be constant regardless of input values, which makes it possible to prevent power-analysis attacks using dependencies between power consumption and intermediate values or operations of the executed cryptographic algorithms. In this paper, we focus on a multiple-valued Binary Carry-Save adder based on the Positive-Digit (PD) number system and its application to RSA processors. The power characteristic of the proposed design is evaluated with HSPICE simulation using 90 nm process technology. The result shows that the proposed design can achieve constant power consumption with lower performance overhead in comparison with the conventional binary design.