For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Automatic Defect Classification System in Semiconductors EDS Test Based on System Entity Structure Methodology
Young-Shin HAN SoYoung KIM TaeKyu KIM Jason J. JUNG
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/07/01
Online ISSN: 1745-1361
Print ISSN: 0916-8532
Type of Manuscript: LETTER
Category: Artificial Intelligence, Data Mining
semiconductor, system entity structure, electrical die sorting, fail bit map data, pruning,
Full Text: PDF(348.9KB)
>>Buy this Article
We exploit a structural knowledge representation scheme called System Entity Structure (SES) methodology to represent and manage wafer failure patterns which can make a significant influence to FABs in the semiconductor industry. It is important for the engineers to simulate various system verification processes by using predefined system entities (e.g., decomposition, taxonomy, and coupling relationships of a system) contained in the SES. For better computational performance, given a certain failure pattern, a Pruned SES (PES) can be extracted by selecting the only relevant system entities from the SES. Therefore, the SES-based simulation system allows the engineers to efficiently evaluate and monitor semiconductor data by i) analyzing failures to find out the corresponding causes and ii) managing historical data related to such failures.