Comparisons of Synchronous-Clocking SFQ Adders

Naofumi TAKAGI  Masamitsu TANAKA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E93-C   No.4   pp.429-434
Publication Date: 2010/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E93.C.429
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Section on Frontiers of Superconductive Electronics)
Category: 
Keyword: 
single-flux-quantum (SFQ) circuit,  adder,  hardware algorithm,  

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Summary: 
Recent advances of superconducting single-flux-quantum (SFQ) circuit technology make it attractive to investigate computing systems using SFQ circuits, where arithmetic circuits play important roles. In order to develop excellent SFQ arithmetic circuits, we have to design or select their underlying algorithms, called hardware algorithms, from different point of view than CMOS circuits, because SFQ circuits work by pulse logic while CMOS circuits work by level logic. In this paper, we compare implementations of hardware algorithms for addition by synchronous-clocking SFQ circuits. We show that a set of individual bit-serial adders and Kogge-Stone adder are superior to others.