Boosted Bit Line Program Scheme for Low Operating Voltage MLC NAND Flash Memory

Youngsun SONG  Ki-Tae PARK  Myounggon KANG  Yunheub SONG  Sungsoo LEE  Youngho LIM  Kang-Deog SUH 

Publication
IEICE TRANSACTIONS on Electronics  Vol.E93-C  No.3  pp.423-425
Publication Date: 2010/03/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Electronic Circuits
Keyword: 
bit line,  coupling capacitance,  Vpass window margin,  boosted channel, 

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Summary: 
A boosted bit line program scheme is proposed for low operating voltage in the multi-level-cell (MLC) NAND flash memory. Our BL to BL boosting scheme, which uses the BL coupling capacitance, is applied to achieve a higher channel potential than is possible with Vcc, so that the Vpass window margin is improved by up to 59% in 40 nm MLC NAND flash memory with 2.7 V Vcc. In the case of 1.8 V Vcc, the margin of the proposed scheme is 12% higher than one of the conventional schemes at 2.7 V Vcc.