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A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique
Koichi ONO Takeshi OHKAWA Masahiro SEGAMI Masao HOTTA
IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
ADC, folding, interpolation, reset, averaging, error correction,
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A 7 bit 1.0 Gsps Cascaded Folding ADC is presented. This ADC employs cascaded folding architecture with 3-degree folders. A new reset technique and layout shuffling enable the ADC to operate at high-speed with low power consumption. Implemented in a 90 nm CMOS process technology the ADC consumes 230 mW with 1.2 V and 2.5 V supplies and has a SNR of 38 dB.