Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network

Xiao PENG  Zhixiang CHEN  Xiongxin ZHAO  Fumiaki MAEHARA  Satoshi GOTO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E93-C   No.3   pp.270-278
Publication Date: 2010/03/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E93.C.270
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
permutation,  banyan network,  LDPC decoder,  reconfigurable,  

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Summary: 
Since the structured quasi-cyclic low-density parity-check (QC-LDPC) codes for most modern wireless communication systems include multiple code rates, various block lengths, and the corresponding different sizes of submatrices in parity check matrix (PCM), the reconfigurable LDPC decoder is desirable and the permutation network is needed to accommodate any input number (IN) and shift number (SN) for cyclic shift. In this paper, we propose a novel permutation network architecture for the reconfigurable QC-LDPC decoders based on Banyan network. We prove that Banyan network has the nonblocking property for cyclic shift when the IN is power of 2, and give the control signal generating algorithm. Through introducing the bypass network, we put forward the nonblocking scheme for any IN and SN. In addition, we present the hardware design of the control signal generator, which can greatly reduce the hardware complexity and latency. The synthesis results using the TSMC 0.18 µm library demonstrate that the proposed permutation network can be implemented with the area of 0.546 mm2 and the frequency of 292 MHz.