For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design
Shintaro IZUMI Takashi TAKEUCHI Takashi MATSUDA Hyeokjong LEE Toshihiro KONISHI Koh TSURUDA Yasuharu SAKAI Hiroshi KAWAGUCHI Chikara OHTA Masahiko YOSHIMOTO
IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
cross-layer design, sensor networks, sensor node, MAC protocol, time synchronization, low power,
Full Text: PDF(1.6MB)>>
This paper presents an ultra-low-power single-chip sensor-node VLSI for wireless-sensor-network applications. A communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. The sensor-node LSI features a synchronous media access control (MAC) protocol and integrates a transceiver, i8051 microcontroller, and dedicated MAC processor. The test chip occupies 33 mm2 in a 180-nm CMOS process, including 1.38 M transistors. It dissipates 58.0 µW under a network environment.