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SAR ADC Algorithm with Redundancy and Digital Error Correction
Tomohiko OGAWA Haruo KOBAYASHI Yosuke TAKAHASHI Nobukazu TAKAI Masao HOTTA Hao SAN Tatsuji MATSUURA Akira ABE Katsuyoshi YAGI Toshihiko MORI
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/02/01
Online ISSN: 1745-1337
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
SAR ADC, digital error correction, non-binary, redundancy,
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This paper describes an algorithm for Successive Approximation Register (SAR) ADCs with overlapping steps that allow comparison decision errors (due to, such as DAC incomplete settling) to be digitally corrected. We generalize this non-binary search algorithm, and clarify which decision errors it can digitally correct. This algorithm requires more SAR ADC conversion steps than a binary search algorithm, but we show that the sampling speed of an SAR ADC using this algorithm can be faster than that of a conventional binary-search SAR ADC -- because the latter must wait for the settling time of the DAC inside the SAR ADC.