An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques

Daehwa PAIK  Yusuke ASADA  Masaya MIYAHARA  Akira MATSUZAWA  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E93-A   No.2   pp.402-414
Publication Date: 2010/02/01
Online ISSN: 1745-1337
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
analog-to-digital converter,  cyclic background calibration,  self-calibration,  interpolation,  

Full Text: PDF(1.1MB)
>>Buy this Article

This paper describes a flash ADC using interpolation (IP) and cyclic background self-calibrating techniques. The proposed IP technique that is cascade of capacitor IP and gate IP with dynamic double-tail latched comparator reduces non-linearity, power consumption, and occupied area. The cyclic background self-calibrating technique periodically suppresses offset mismatch voltages caused by static fluctuation and dynamic fluctuation due to temperature and supply voltage changes. The ADC has been fabricated in 90-nm 1P10M CMOS technology. Experimental results show that the ADC achieves SNDR of 6.07 bits without calibration and 6.74 bits with calibration up to 500 MHz input signal at sampling rate of 600 MSps. It dissipates 98.5 mW on 1.2-V supply. FoM is 1.54 pJ/conv.