Design for Delay Fault Testability of 2-Rail Logic Circuits

Kentaroh KATOH  Kazuteru NAMBA  Hideo ITO 

Publication
IEICE TRANSACTIONS on Information and Systems  Vol.E92-D  No.2  pp.336-341
Publication Date: 2009/02/01
Online ISSN: 1745-1361
Print ISSN: 0916-8532
Type of Manuscript: LETTER
Category: Dependable Computing
Keyword: 
2-rail logic circuits,  design for testability,  delay fault testing,  scan design,  set-reset operation, 

Full Text: PDF(455.1KB)

Summary: 
This paper presents a scan design for delay fault testability of 2-rail logic circuits. The flip flops used in the scan design are based on master-slave ones. The proposed scan design provides complete fault coverage in delay fault testing of 2-rail logic circuits. In two-pattern testing with the proposed scan design, initial vectors are set using the set-reset operation, and the scan-in operation for initial vectors is not required. Hence, the test application time is reduced to about half that of the enhanced scan design. Because the additional function is only the set-reset operation of the slave latch, the area overhead is small. The evaluation shows that the differences in the area overhead of the proposed scan design from those of the standard scan design and the enhanced scan design are 2.1 and -14.5 percent on average, respectively.