Pipelining a Multi-Mode SHA-384/512 Core with High Area Performance Rate

Anh-Tuan HOANG  Katsuhiro YAMAZAKI  Shigeru OYANAGI  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E92-D   No.10   pp.2034-2042
Publication Date: 2009/10/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E92.D.2034
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: VLSI Systems
Keyword: 
cryptography,  SHA-2,  fine-grained pipelining,  FPGA,  

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Summary: 
The security hash algorithm 512 (SHA-512), which is used to verify the integrity of a message, involves computational iterations on data. The huge computation delay generated in such iterations limits the entire throughput of the system and makes it difficult to pipeline the computation. We describe a way to pipeline the computation using fine-grained pipelining with balanced critical paths. In this method, one critical path is broken into two stages by using data forwarding. The other critical path is broken into three stages by using computation postponement. The resulting critical paths all have two adder-layers with some data movements, and thus are balanced. In addition, the method also allows register reduction. Also, the similarity in SHA-384 and SHA-512 are used for a multi-mode design, which can generate a message digest for both versions with the same throughput, but with only a small increase in hardware size. Experimental results show that our implementation achieved not only the best area performance rate (throughput divided by area), but also a higher throughput than almost all related work.