High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer

Yu-Lung LO  Wei-Bin YANG  Ting-Sheng CHAO  Kuo-Hsing CHENG 

Publication
IEICE TRANSACTIONS on Electronics  Vol.E92-C  No.6  pp.890-893
Publication Date: 2009/06/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Electronic Circuits
Keyword: 
dynamic D flip-flops,  counters,  prescalers,  ultra-low-voltage design, 

Full Text: PDF(516KB)

Summary: 
A high-speed and ultra-low-voltage divide-by-4/5 counter with dynamic floating input D flip-flop (DFIDFF) is presented in this paper. The proposed DFIDFF and control logic gates are merged to reduce effective capacitance of internal and external nodes, and increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-µm CMOS process. The measured maximum operating frequency and power consumption of the counter are 600 MHz and 8.35 µW at a 0.5 V supply voltage. HSPICE simulations demonstrate that the proposed counter (divide-by-4) reduces power-delay product (PDP) by 37%, 71%, and 57% from those of the TGFF counter, Yang's counter [1], and the E-TSPC counter [2], respectively.