Duty Cycle Corrector for Pipelined ADC with Low Added Jitter

Zhengchang DU  Jianhui WU  Shanli LONG  Meng ZHANG  Xincun JI 

Publication
IEICE TRANSACTIONS on Electronics  Vol.E92-C  No.6  pp.864-866
Publication Date: 2009/06/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
duty cycle,  pipelined ADC,  continuous-time integrator,  low added jitter, 

Full Text: PDF(80.8KB)

Summary: 
A wide range, low jitter Duty Cycle Corrector (DCC) based on continuous-time integrator is proposed. It introduces little added jitter in the sampling edge, which make it good candidate for pipelined ADC application. The circuit is implemented in CMOS 0.35 µm 2P4M Mixed Signal process. The experimental results show the circuit can work for a wide frequency range from 500 kHz to 280 MHz, with a correction error within 50%1% under 200 MHz, and the acceptable duty cycle can be as wide as 1-99% for low frequency inputs.