Scalability of Vertical MOSFETs in Sub-10 nm Generation and Its Mechanism

Tetsuo ENDOH  Yuto NORIFUSA 

Publication
IEICE TRANSACTIONS on Electronics  Vol.E92-C  No.5  pp.594-597
Publication Date: 2009/05/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
Vertical MOSFET,  sub-10 nm,  driving current,  cutoff leakage current,  current density, 

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Summary: 
In this paper, the device performances of sub-10 nm Vertical MOSFETs are investigated. One of the drawbacks of conventional planar MOSFETs is that in the sub-10 nm generation, its cutoff leakage current increases due to the short channel effects, but even more, its driving current decreases due to the quantum mechanical confinement effects such as the sub-band effect and the depletion of the inversion layer. It is shown for the first time that by downscaling the silicon pillar diameter from 20 nm to 4 nm, the Vertical MOSFET increases its driving current per footprint to about 2 times and suppresses its total cutoff leakage current per footprint to less than 1/60 at the same time. Moreover, the mechanisms of these improvements of Vertical MOSFET performances are clarified. The results of this work show that Vertical MOSFETs can overcome the drawbacks of conventional planar MOSFETs and achieve the high device performance through the sub-10 nm generation.