A Way Enabling Mechanism Based on the Branch Prediction Information for Low Power Instruction Cache

Gi-Ho PARK  Jung-Wook PARK  Hoi-Jin LEE  Gunok JUNG  Sung-Bae PARK  Shin-Dug KIM 

Publication
IEICE TRANSACTIONS on Electronics  Vol.E92-C  No.4  pp.517-521
Publication Date: 2009/04/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
way-enabling mechanism,  branch information,  embedded processor and low power instruction cache design, 

Full Text: PDF(515KB)

Summary: 
This paper presents a cache way enabling mechanism using branch target addresses. This mechanism uses branch prediction information to avoid the power consumption due to unnecessary cache way access by enabling only the cache way(s) that should be accessed. The proposed cache way enabling mechanism reduces the power consumption of the instruction cache by 63% without any performance degradation of the processor. An ARM1136 processor simulator and the Synopsys PrimeTime are used to perform the performance/power simulation and static timing analysis of the proposed mechanisms respectively.