Development of an Enterprise-Wide Yield Management System Using Critical Area Analysis for High-Product-Mix Semiconductor Manufacturing

Yuichi HAMAMURA  Chizu MATSUMOTO  Yoshiyuki TSUNODA  Koji KAMODA  Yoshio IWATA  Kenji KANAMITSU  Daisuke FUJIKI  Fujihiko KOJIKA  Hiromi FUJITA  Yasuo NAKAGAWA  Shun'ichi KANEKO 

Publication
IEICE TRANSACTIONS on Electronics  Vol.E92-C  No.1  pp.144-152
Publication Date: 2009/01/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Semiconductor Materials and Devices
Keyword: 
defects,  failure analysis,  yield estimation,  integrated circuit layout,  simulation, 

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Summary: 
To improve product yield in high-product-mix semiconductor manufacturing, it is important to estimate the systematic yield inherent to each product and to extract problematic products that have low systematic yields. We propose a simplified and available yield model using a critical area analysis. This model enables the extraction of problematic products by the relationship between actual yields and the short sensitivities of the products. Furthermore, we present an enterprise-wide yield management system using this model and some useful applications. As a result, the system increases the efficiency of the yield management and enhancement dramatically.