Interacting Self-Timed Pipelines and Elementary Coupling Control Modules

Kazuhiro KOMATSU  Shuji SANNOMIYA  Makoto IWATA  Hiroaki TERADA  Suguru KAMEDA  Kazuo TSUBOUCHI 

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences  Vol.E92-A  No.7  pp.1642-1651
Publication Date: 2009/07/01
Online ISSN: 1745-1337
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword: 
self-timed pipeline,  flow-thru processing,  interacting pipelines,  VLSI/SoC architecture, 

Full Text: PDF(883.3KB)

Summary: 
The self-timed pipeline (STP) is one of the most promising VLSI/SoC architectures. It achieves efficient utilization of tens of billions of transistors, consumes ultra low power, and is easy-to-design because of its signal integrity and low electro-magnetic interference. These basic features of the STP have been proven by the development of self-timed data-driven multimedia processors, DDMP's. This paper proposes a novel scheme of interacting self-timed (clockless) pipelines by which the various distributed and interconnected pipelines can achieve highly functional stream processing in future giga-transistor chips. The paper also proposes a set of elementary coupling control modules that facilitate various combinations of flow-thru processing between pipelines, and then discusses the practicality of the proposed scheme through the LSI design of application modules such as a priority-based queue, a mutual interconnection network, and a pipelined sorter.