Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures

Shan ZENG  Wenjian YU  Jin SHI  Xianlong HONG  Chung-Kuan CHENG 

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences  Vol.E92-A  No.6  pp.1476-1484
Publication Date: 2009/06/01
Online ISSN: 1745-1337
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword: 
high-frequency effect,  inductance modeling,  parasitic extraction,  partial reluctance,  power/ground grid, 

Full Text: PDF(672.4KB)

Summary: 
Inductive effect becomes important for on-chip global interconnects, like the power/ground (P/G) grid. Because of the locality property of partial reluctance, the inverse of partial inductance, the window-based partial reluctance extraction has been applied for large-scale interconnect structures. In this paper, an efficient method of partial reluctance extraction is proposed for large-scale regular P/G grid structures. With a block reuse technique, the proposed method makes full use of the structural regularity of the P/G grid. Numerical results demonstrate the proposed method is able to efficiently handle a P/G grid with up to one hundred thousands wire segments. It is several tens times faster than the window-based method, while generating accurate frequency-dependent partial reluctance and resistance.