Finite Input-Memory Automaton Based Checker Synthesis of SystemVerilog Assertions for FPGA Prototyping

Chengjie ZANG  Shinji KIMURA 

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences  Vol.E92-A  No.6  pp.1454-1463
Publication Date: 2009/06/01
Online ISSN: 1745-1337
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword: 
SystemVerilog Assertion,  assertion checker,  finite input-memory automaton, 

Full Text: PDF(260.5KB)

Summary: 
Checker synthesis for assertion based verification becomes popular because of the recent progress on the FPGA prototyping environment. In the paper, we propose a checker synthesis method based on the finite input-memory automaton suitable for embedded RAM modules in FPGA. There are more than 1 Mbit memories in medium size FPGA's and such embedded memory cells have the capability to be used as the shift registers. The main idea is to construct a checker circuit using the finite input-memory automata and implement shift register chain by logic elements or embedded RAM modules. When using RAM module, the method does not consume any logic element for storing the value. Note that the shift register chain of input memory can be shared with different assertions and we can reduce the hardware resource significantly. We have checked the effectiveness of the proposed method using several assertions.