Analysis and Modeling of Leakage Current for Four-Terminal MOSFET in Off-State and Low Leakage Switches

Kawori TAKAKUBO  Toru ETO  Hajime TAKAKUBO  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E92-A   No.2   pp.421-429
Publication Date: 2009/02/01
Online ISSN: 1745-1337
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
MOSFET in off-state,  low leakage current,  body effect,  four-terminal MOSFET,  MOSFET switch,  

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Leakage current for MOSFET in off-state is one of the serious problems in charge-based analog circuits under low power supply. To suppress the leakage current, a method that a slight voltage is applied to source to accomplish reverse bias between source and bulk is proposed. The proposed bias condition, also other bias conditions, is analyzed by injection carrier density in p-n junction and surface carrier concentration in MOS diode in four-terminal MOSFET. Leakage current is modeled by combining the characteristics of p-n junction with MOS diode in MOSFET. The characteristics of MOSFET fabricated with a standard 0.18 µm n-well CMOS technology are measured to investigate the basic principle. Measured leakage current fits to the theoretical leakage current exactly. The proposed slight bias to source terminal in MOSFET is proved most efficient to reduce the leakage current. Based on the proposed source bias condition, MOSFET switches with low leakage current under a single power supply are proposed.