Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System

Shu-Yu JIANG  Chan-Wei HUANG  Yu-Lung LO  Kuo-Hsing CHENG 

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences  Vol.E92-A  No.2  pp.389-400
Publication Date: 2009/02/01
Online ISSN: 1745-1337
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
built-in jitter measurement,  Vernier caliper,  equivalent-signal sampling,  auto focus, 

Full Text: PDF(1.2MB)

Summary: 
Several problems in built-in-jitter-measurement (BIJM) system designs have been identified in recent years. The problems are associated with the external low-jitter sampling clock, chip area, timing resolution, or the measurement range via the process voltage temperature (PVT) variation effect. In this work, there are three proposed approaches and one conventioanl method that improve BIJM systems. For the system level, a proposed real equivalent-signal sampling technique is utilized to clear the requirement of the external low-jitter sampling clock. The proposed Vernier caliper structure is applied to reduce chip area cost for the designated timing resolution. At the circuit level, the proposed auto focus technique eliminates the PVT variation effect for the measurement range. The stepping scan technique is the conventional method that employed to minimize the area cost of counter circuits. All of these techniques were implemented in the 0.35 µm CMOS process. Furthermore, these techniques are successfully verified in 14 ps circuit resolution and a 500*750 µm chip area for the 100-400 MHz measurement range.