A 0.027-mm2 Self-Calibrating Successive Approximation ADC Core in 0.18-µm CMOS


IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E92-A   No.2   pp.360-366
Publication Date: 2009/02/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E92.A.360
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
analog to digital converter,  charge redistribution type digital to analog converter,  successive approximation architecture,  calibration technique,  

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We present a 10-bit 1-MS/s successive approximation analog-to-digital converter core including a charge redistribution digital-to-analog converter and a comparator. A new linearity calibration technique enables use of a nearly minimum capacitor limited by kT/C noise. The ADC core without digital control blocks has been fabricated in a 0.18-µm CMOS process and consumes 118 µW at 1.8 V power supply. Also, the active area of ADC core is realized to be 0.027 mm2. The calibration improves the SNDR by 13.4 dB and the SFDR by 21.0 dB. The measured SNDR and SFDR at 1 kHz input are 55.2 dB and 73.2 dB respectively.