Complexity-Reducing Algorithm for Serial Scheduled Min-Sum Decoding of LDPC Codes

Hironori UCHIKAWA  Kohsuke HARADA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E92-A   No.10   pp.2411-2417
Publication Date: 2009/10/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E92.A.2411
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Information Theory and Its Applications)
Category: Coding Theory
Keyword: 
low-density parity-check codes,  min-sum decoding,  serial scheduling,  and complexity,  

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Summary: 
We propose a complexity-reducing algorithm for serial scheduled min-sum decoding that reduces the number of check nodes to process during an iteration. The check nodes to skip are chosen based on the reliability, a syndrome and a log-likelihood-ratio (LLR) value, of the incoming messages. The proposed algorithm is evaluated by computer simulations and shown to reduce the decoding complexity about 20% compared with a conventional serial scheduled min-sum decoding with small fractional decibel degradation in error correction performance.