Resource and Performance Evaluations of Fixed Point QRD-RLS Systolic Array through FPGA Implementation

Yoshiaki YOKOYAMA  Minseok KIM  Hiroyuki ARAI  

Publication
IEICE TRANSACTIONS on Communications   Vol.E91-B   No.4   pp.1068-1075
Publication Date: 2008/04/01
Online ISSN: 1745-1345
DOI: 10.1093/ietcom/e91-b.4.1068
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Wireless Communication Technologies
Keyword: 
systolic array,  QR decomposition,  RLS,  CORDIC,  FPGA,  

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Summary: 
At present, when using space-time processing techniques with multiple antennas for mobile radio communication, real-time weight adaptation is necessary. Due to the progress of integrated circuit technology, dedicated processor implementation with ASIC or FPGA can be employed to implement various wireless applications. This paper presents a resource and performance evaluation of the QRD-RLS systolic array processor based on fixed-point CORDIC algorithm with FPGA. In this paper, to save hardware resources, we propose the shared architecture of a complex CORDIC processor. The required precision of internal calculation, the circuit area for the number of antenna elements and wordlength, and the processing speed will be evaluated. The resource estimation provides a possible processor configuration with a current FPGA on the market. Computer simulations assuming a fading channel will show a fast convergence property with a finite number of training symbols. The proposed architecture has also been implemented and its operation was verified by beamforming evaluation through a radio propagation experiment.