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Post-Silicon Clock-Timing Tuning Based on Statistical Estimation
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E91-A No.9 pp.2322-2327
Publication Date: 2008/09/01
Online ISSN: 1745-1337
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
post-silicon clock-timing tuning,
programmable delay element (PDE),
Full Text: PDF(573.6KB)
In deep-submicron technologies, process variations can significantly affect the performance and yield of VLSI chips. As a countermeasure to the variations, post-silicon tuning has been proposed. Deskew, where the clock timing of flip-flops (FFs) is tuned by inserted programmable delay elements (PDEs) into the clock tree, is classified into this method. We propose a novel deskew method that decides the delay values of the elements by measuring a small amount of FFs' clock timing and presuming the rest of FFs' clock timings based on a statistical model. In addition, our proposed method can determine the discrete PDE delay value because the rewriting constraint satisfies the condition of total unimodularity.