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A HighSpeed Design of Montgomery Multiplier
Yibo FAN Takeshi IKENAGA Satoshi GOTO
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E91A
No.4
pp.971977 Publication Date: 2008/04/01
Online ISSN: 17451337 Print ISSN: 09168508 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: Montgomery multiplier, highspeed, highradix, scalable,
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Summary:
With the increase of key length used in public cryptographic algorithms such as RSA and ECC, the speed of Montgomery multiplication becomes a bottleneck. This paper proposes a high speed design of Montgomery multiplier. Firstly, a modified scalable highradix Montgomery algorithm is proposed to reduce critical path. Secondly, a highradix clocksaving dataflow is proposed to support highradix operation and one clock cycle delay in dataflow. Finally, a hardwarereused architecture is proposed to reduce the hardware cost and a parallel radix16 design of data path is proposed to accelerate the speed. By using HHNEC 0.25 µm standard cell library, the implementation results show that the total cost of Montgomery multiplier is 130 KGates, the clock frequency is 180 MHz and the throughput of 1024bit RSA encryption is 352 kbps. This design is suitable to be used in high speed RSA or ECC encryption/decryption. As a scalable design, it supports any keylength encryption/decryption up to the size of onchip memory.

