For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Advanced Assertion-Based Design for Mixed-Signal Verification
Alexander JESSER Stefan LAEMMERMANN Alexander PACHOLIK Roland WEISS Juergen RUF Lars HEDRICH Wolfgang FENGLER Thomas KROPF Wolfgang ROSENSTIEL
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Online ISSN: 1745-1337
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
assertions-based verification, mixed-signal simulation, simulation-based property checking, mixed-signal assertions, dynamic verification,
Full Text: PDF(765.8KB)
>>Buy this Article
Functional and formal verification are important methodologies for complex mixed-signal design validation. However the industry is still verifying such systems by pure simulation. This process lacks on error localization and formal verifications methods. This is the existing verification gap between the analog and digital blocks within a mixed-signal system. Our approach improves the verification process by creating temporal properties named mixed-signal assertions which are described by a combination of digital assertions and analog properties. The proposed method is a new assertion-based verification flow for designing mixed-signal circuits. The effectiveness of the approach is demonstrated on a Σ/Δ-converter.