Low-Voltage Embedded RAMs in Nanometer Era

Takayuki KAWAHARA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E90-C   No.4   pp.735-742
Publication Date: 2007/04/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.4.735
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: 
Keyword: 
low-voltage,  SRAM,  DRAM,  FD-SOI,  twin-cell,  embedded RAM,  

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Summary: 
Low-voltage nanometer-scale embedded RAM cells are described. First, low-voltage RAM cells are compared in terms of cell size, threshold voltage for MOS transistor, and signal charge. Second, the solution for 6T and 4T SRAM cells to widen the voltage margin are investigated, especially the advantages with a back-gate controlled thin buried-oxide fully-depleted (FD) SOI are presented. Then, DRAM approach with a novel twin-cell is discussed in terms of improving the retention time and low-voltage operation. These low-voltage cell technologies are the promising candidates for future embedded RAMs.