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Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes
Yasuhiro MORITA Hidehiro FUJIWARA Hiroki NOGUCHI Yusuke IGUCHI Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: Next-Generation Memory for SoC
6T SRAM cell, 8T SRAM cell, Vth variation,
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This paper shows that an 8T SRAM cell is superior to a 6T cell in terms of cell area in a future process. At a 65-nm node and later, the 6T cell comprised of the minimum-channel-length transistors cannot make the minimum area because of threshold-voltage variation. In contrast, the 8T cell can employ the optimized transistors and achieves the minimum area even if it is used as a single-port SRAM. In a 32-nm process, the 8T-cell area is smaller than the 6T cell by 14.6% at a supply voltage of 0.8 V. We also discuss the area and access time comparisons between the 6T-SRAM and 8T-SRAM macros.