A 90 nm 4848 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations

Kazutoshi KOBAYASHI  Kazuya KATSUKI  Manabu KOTANI  Yuuri SUGIHARA  Yohei KUME  Hidetoshi ONODERA 

Publication
IEICE TRANSACTIONS on Electronics  Vol.E90-C  No.10  pp.1919-1926
Publication Date: 2007/10/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: Low-Power and High-Performance VLSI Circuit Technology
Keyword: 
variation-aware,  reconfigurable device,  FPGA,  yield,  DFM, 

Full Text: PDF(690.4KB)

Summary: 
We have fabricated a LUT-based FPGA device with functionalities measuring within-die variations in a 90 nm process. Variations are measured using ring oscillators implemented as a configuration of the FPGA. Random variations are dominant in a 4848 configurable array laid out in a 3 mm3 mm square region. It has a functionality to measure delays on actual signal paths between flip flops by providing two clock pulses. Measured variations are used to maximize the operating frequency of each device by choosing the optimal paths. Optimizations of routing paths using a simple model circuit reveals that performance of the circuit is enhanced by 2.88% in average and a maximum of 9.34%.