Key Technologies for Miniaturization and Power Reduction of Analog-to-Digital Converters for Video Use

Masao HOTTA  Tatsuji MATSUURA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E89-C   No.6   pp.664-672
Publication Date: 2006/06/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.6.664
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
analog-to-digital converter,  ADC,  pipeline,  time-interleaving,  self-calibration and look-ahead pipeline,  

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Summary: 
Analog-to-Digital converters (ADCs) for video applications have made exciting progress in miniaturization and power reduction in the past 20 years. This paper mainly describes the key technologies for miniaturization and power reduction of 10-bit video-frequency ADCs. By reviewing useful architectures and circuit schemes for video-frequency ADCs, self-calibration techniques and interleaving techniques are surveyed. The subranging pipeline look-ahead ADC architecture is introduced. It has a potential for reducing power consumption and improving conversion rate when minute deep submicron CMOS devices are used with low supply voltage.