For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs
Kenji SHIMAZAKI Makoto NAGATA Mitsuya FUKAZAWA Shingo MIYAHARA Masaaki HIRATA Kazuhiro SATOH Hiroyuki TSUJIKAWA
IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
power-supply noise, ground noise, noise detector, dynamic IR drop, timing analysis,
Full Text: PDF(1.6MB)
>>Buy this Article
We propose a semi-dynamic timing analysis flow applicable to large-scale circuits that takes into account dynamic power-supply drop. Logic delay is accurately estimated in the presence of power-supply noise through timing correction as a function of power-supply voltage during operation, where a time-dependent power-supply noise waveform is derived by way of a vectorless technique. Measurements and analysis of dynamic supply-noise waveforms and associated delay changes were performed on a sub-100-nm CMOS test circuit with embedded on-chip noise detectors and delay monitors. The proposed analysis technique was extended and applied to a test digital circuit with more than 10 million gates and validated toward a multi-10-million-gate CMOS SoC design.