Coding Floorplans with Fewer Bits

Katsuhisa YAMANAKA  Shin-ichi NAKANO 

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences  Vol.E89-A  No.5  pp.1181-1185
Publication Date: 2006/05/01
Online ISSN: 1745-1337
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
graphs,  algorithms, 

Full Text: PDF(182.3KB)

Summary: 
A naive coding of floorplans needs 2m bits for each floorplan. In this paper we give a new simple coding of floorplans, which needs only 5m/3 bits for each floorplan.