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Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an LSI Chip
IEICE TRANSACTIONS on Electronics Vol.E88-C No.5 pp.788-795
Publication Date: 2005/05/01
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Microelectronic Test Structures)
within-die parameter variation,
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We propose guidelines for LSI-chip design, taking the within-die variations into consideration, and for process quality improvement to suppress the variations. The auto-correlation length, λ, of device variation is shown to be a useful measure to treat the systematic variations in a chip. We may neglect the systematic variation in chips within the range of λ, while σ2 of the systematic variation must be added to σ2 of the random variation outside the λ. The random variations, on the other hand, exhibit complete randomness even in the closest pair transistors. The mismatch variations in transistor pairs were enhanced by 1.41(=) compared with the random variations in single transistors. This requires careful choice of gate size in designing a transistor pair with a minimum size, such as transfer gates in an SRAM cell. Poly-Si gate formation is estimated to be the most important process to ensure the spatial uniformity in transistor current and to enhance circuit performance. Large relative variations are observed for the contact to p+ diffusion, via1 (M1-M2), and via2 (M2-M3) among parameter variations in passive elements. The standard deviations for random variations in via1 and via2 are noticeably widespread, indicating the importance of the via resistance control in BEOL. The spatial frequency power spectrum for within-die random variations is confirmed experimentally, as uniform ('white') with respect to the spatial frequency. To treat the large 'white random noise,' the least-square method with a 4th-order polynomial exhibits a best efficiency as a fitting function for decomposing the raw variation data into systematic part and random part.