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Design Techniques of Delay-Locked Loop for Jitter Minimization in DRAM Applications
IEICE TRANSACTIONS on Electronics Vol.E88-C No.4 pp.753-759
Publication Date: 2005/04/01
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
Full Text: PDF(938KB)
High performance delay-locked loop (DLL) is key to the high data rate chip-to-chip communication, suggesting the output jitter, due to power noise, bang-bang noise, temperature-voltage drift, etc, should be properly controlled. In this paper, high speed DRAM operation can be achieved by a dual loop DLL with various novel techniques; a new counting code with hysteretic bit-transitions can remove the large DAC glitches by preventing the binary bit-transitions in the locking states. A delay buffer, which is insensitive to the power supply fluctuations, is proposed. The voltage-temperature (VT) dependencies of the feedback path and the open clock path are balanced, minimizing the VT shift of the clock. As a result, the high-speed DRAM interface with the maximized setup/hold window can be accomplished.