Layout-Based Detection Technique of Line Pairs with Bridging Fault Using IDDQ

Masaru SANADA 

Publication
IEICE TRANSACTIONS on Information and Systems  Vol.E87-D  No.3  pp.557-563
Publication Date: 2004/03/01
Online ISSN: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Fault Detection
Keyword: 
IDDQ,  bridging fault,  logic,  layout structure,  fault diagnosis, 

Full Text: PDF(3MB)

Summary: 
Abnormal IDDQ (Quiescent power supply current) is the signal to indicate the existence of physical damage which includes the between circuit lines. Using this signal, a CAD-based line pairs with bridging fault (LBFs) detection technique has been developed to enhance the manufacturing yield of advanced logic LSI with scaled-down structure and multi-metal layers. The proposed technique progressively narrows the doubtful LBFs down by logic information and layout structure. This technique, quickly handled, is applied to draw down the distribution chart of bridging fault portion on wafer, the feature of which chart is fed back to manufacturing process and layout design.