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Generation of Test Sequences with Low Power Dissipation for Sequential Circuits
Yoshinobu HIGAMI Shin-ya KOBAYASHI Yuzo TAKAMATSU
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Test Generation and Compaction
LSI testing, sequential circuit, test generation, low power dissipation, stuck-at fault,
Full Text: PDF(176KB)>>
When LSIs that are designed and manufactured for low power dissipation are tested, test vectors that make the power dissipation low should be applied. If test vectors that cause high power dissipation are applied, incorrect test results are obtained or circuits under test are permanently damaged. In this paper, we propose a method to generate test sequences with low power dissipation for sequential circuits. We assume test sequences generated by an ATPG tool are given, and modify them while keeping the original stuck-at fault coverages. The test sequence is modified by inverting the values of primary inputs of every test vector one by one. In order to keep the original fault coverage, fault simulation is conducted whenever one value of primary inputs is inverted. We introduce heuristics that perform fault simulation for a subset of faults during the modification of test vectors. This helps reduce the power dissipation of the modified test sequence. If the fault coverage by the modified test sequence is lower than that by the original test sequence, we generate a new short test sequence and add it to the modified test sequence.