Circuit Partition and Reordering Technique for Low Power IP Design

Kun-Lin TSAI  Shanq-Jang RUAN  Chun-Ming HUANG  Edwin NAROSKA  Feipei LAI  

IEICE TRANSACTIONS on Electronics   Vol.E87-C   No.4   pp.613-620
Publication Date: 2004/04/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
low power,  state reordering,  circuit partition,  entropy,  

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Circuit partition, retiming and state reordering techniques are effective in reducing power consumption of circuits. In this paper, we propose a partition architecture and a methodology to reduce power consumption when designing low power IP, named PRC (Partition and Reordering Circuit). The circuit reordering synthesis flow consists of three phases: first, evenly partition the circuit based on the Shannon expansion; secondly encode the output vectors of each partition to build an equivalent functional logic. Finally, apply reordering algorithm to reorganize the logic function to reduce power consumption and decrease area cost. The validity of our architecture is proven by applying it to MCNC benchmark with simulation environment.