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Digital/Analog Hybrid Implementation of Cardinal Spline Interpolation
Masaru KAMADA Mitsuhiro MATSUO
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/09/01
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Digital Signal Processing
spline interpolation, digital-to-analog conversion, sampled-data feedback control,
Full Text: PDF(291.9KB)
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A digital/analog hybrid system is presented which implements the cardinal polynomial spline interpolation of arbitrary degree. Based on the fact that the (m-1)st derivative of a spline of degree m-1 is a staircase function, this system generates a cardinal spline of degree m-1 by m-1 cascaded integrators with a staircase function input. A given sequence of sampled values are transformed by a digital filter into coefficients for the B-spline representation of the spline interpolating the sampled values. The values of its (m-1)st derivative with respect to time are computed by the recurrence formula interpreting differentiation of the spline as difference of the coefficients. Then a digital-to-analog converter generates a staircase function representing the (m-1)st derivative, which is integrated by a cascade of m-1 analog integrators to make the expected spline. In order to cope with the offset errors involved in the integrators, a dynamical sampled-data control is attached. An analog-to-digital converter is employed to sample the output of the cascaded integrators. Target state of the cascaded integrators at each sampling instance is computed from the coefficients for the B-spline representation. The state error between the target and the estimated is compensated by feeding back a weighted sum of the state error to the staircase input.