Timing Optimization Methodology Based on Replacing Flip-Flops by Latches

Ko YOSHIKAWA  Keisuke KANAMARU  Yasuhiko HAGIHARA  Shigeto INUI  Yuichi NAKAMURA  Takeshi YOSHIMURA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E87-A   No.12   pp.3151-3158
Publication Date: 2004/12/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic synthesis,  sequential circuit,  timing optimization,  level-sensitive latch,  formal verification,  

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Summary: 
Latch-based circuits have advantages for timing and are widely used for high-speed custom circuits. ASIC design flows, however, are based on circuits with flip-flops. This paper describes a new timing optimization algorithm by replacing the flip-flops in high-end ASICs by latches without changing the functionality of the circuits. Timing is optimized by using a fixed-phase retiming minimizing the impact of clock skew and jitter. A formal equivalence verification method that assures the logical correctness of the latch-replaced circuits is also proposed. Experimental results show that the optimization algorithm decreases the delay of benchmark circuits by as much as 17%.