SoC Architecture Synthesis Methodology Based on High-Level IPs

Michiaki MURAOKA  Hiroaki NISHI  Rafael K. MORIZAWA  Hideaki YOKOTA  Yoichi ONISHI  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E87-A   No.12   pp.3057-3067
Publication Date: 2004/12/01
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
system level design,  architecture synthesis,  high level IP,  CAD,  

Full Text: PDF(3.7MB)
>>Buy this Article


Summary: 
We propose a sophisticated synthesis methodology for SoC (System-on-Chip) architectures from the system level specification based on reusable high-level IPs named as Virtual Cores (VCores), in this paper. This synthesis methodology generates an initial architecture that consists of a CPU, buses, IPs, peripherals, I/Os and an RTOS (Real Time Operating System), as well as making tradeoffs to the architecture, between hardware and software on assigned software VCores and hardware VCores. The results of an architecture level design experiment, using the proposed methodology, shows that the partial automation of the architecture synthesis process, allied with design reuse, accelerates the architecture design, therefore, reducing the time required to design an architecture of SoC.