Signal Transmission and Coding Architecture for Next-Generation Ethernet

Hidehiro TOYODA  Hiroaki NISHI  Shinji NISHIMURA  Hisaaki KANAI  Katsuyoshi HARASAWA  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E86-D   No.11   pp.2317-2324
Publication Date: 2003/11/01
Online ISSN: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on New Technologies in the Internet and their Applications)
Category: 
Keyword: 
100-Gigabit Ethernet,  64B/66B,  skew compensation,  

Full Text: PDF(1.9MB)
>>Buy this Article


Summary: 
The first practical approach to 100-Gigabit Ethernet, i.e., Ethernet with a throughput of 100-Gb/s, is proposed for use in the next generation of LANs for GRID computing and large-capacity data centers. New structures, including a coding architecture, de-skewing method and high-speed packaging techniques, are introduced to the PHY layer to obtain the required data rate. Our form of 100-Gigabit Ethernet uses 10-Gb/s 10-channel CWDM or parallel-optical links. The coding architecture is formed of 64B/66B codes, modified for the CWDM and parallel links. In the de-skewing of the parallel signals, specially designed IDLE characters are used to compensate for skewing of data in the respective signal lanes. Advanced packaging techniques, which suppress the propagation loss and reflection of the 10-Gb/s lanes to obtain high-speed, good integrity and low-noise signaling, are proposed and evaluated. The proposed architectural features make this 100-Gigabit Ethernet concept practical for next-generation LANs.