A 90 mW MPEG-4 Video Codec LSI with the Capability for Core Profile

Takashi HASHIMOTO  Shunichi KUROMARU  Masayoshi TOUJIMA  Yasuo KOHASHI  Masatoshi MATSUO  Toshihiro MORIIWA  Masahiro OHASHI  Tsuyoshi NAKAMURA  Mana HAMADA  Yuji SUGISAWA  Miki KUROMARU  Tomonori YONEZAWA  Satoshi KAJITA  Takahiro KONDO  Hiroki OTSUKI  Kohkichi HASHIMOTO  Hiromasa NAKAJIMA  Taro FUKUNAGA  Hiroaki TOIDA  Yasuo IIZUKA  Hitoshi FUJIMOTO  Junji MICHIYAMA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E86-C   No.7   pp.1374-1384
Publication Date: 2003/07/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 
MPEG-4 visual,  core profile,  hybrid architecture,  clock gating,  embedded DRAM,  low power,  

Full Text: PDF(2.3MB)>>
Buy this Article




Summary: 
A low power MPEG-4 video codec LSI with the capability for core profile decoding is presented. A 16-b DSP with a vector pipeline architecture and a 32-b arithmetic unit, eight dedicated hardware engines to accelerate MPEG-4 SP@L1 codec, CP@L1 decoding and post video processing, 20-Mb embedded DRAM, and three peripheral blocks are integrated together on a single chip. MPEG-4 SP@L1 codec, CP@L1 decoding and post video processing are realized with a hybrid architecture consisting of a programmable DSP and dedicated hardware engines at low operating frequency. In order to reduce the power consumption, clock gating technique is fully adopted in each hardware block and embedded DRAM is employed. The chip is implemented using 0.18-µm quad-metal CMOS technology, and its die area is 8.8 mm 8.6 mm. The power consumption is 90 mW at a SP@L1 codec and 110 mW at a CP@L1 decoding.